Research Developed Using CORNERSTONE Published in Nature Communications

A multifunctional silicon photonics integrated circuit that can be programmed to perform a variety of different functions has been developed by researchers from Spain and the UK. The chip was fabricated within the framework of the CORNERSTONE project.

This is “the first photonic integrated chip that enables multiple functionalities by employing a single common architecture”.

The results have been published in Nature Communications.

Reference: Daniel Pérez, Ivana Gasulla, Lee Crudgington, David J. Thomson, Ali Z. Khokhar, Ke Li, Wei Cao, Goran Z. Mashanovich & José Capmany. Multipurpose silicon photonics signal processor core. Nature Communications 8. doi:10.1038/s41467-017-00714-1.

CORNERSTONE Multi Project Wafer Run 5 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 5 have been announced. The platform is 340 nm Si / 2 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 3 silicon etches of 140 nm (grating couplers), 240 nm (rib waveguides) and 340 nm (strip waveguides). In addition, there will be a 1 µm top cladding SiO2 layer.

The service is free of charge for UK academia. The cost for non-UK academia is £5,000 for a design space of 11.47 mm x 4.9 mm, or £3,500 for a design space of 5.5 mm x 4.9 mm.

More information on this run can be found here.

The mask submission deadline is Friday 12th January 2018.

CORNERSTONE Multi Project Wafer Run 4 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 4 have been announced. There will be:

  • 3 Si etch processes:

1) a shallow Si etch of 70 nm (grating couplers),

2) an intermediate Si etch of 120 nm (rib waveguides), and

3) a continuation Si etch of a further 100 nm to the BOX layer (strip waveguides).

  • 4 Si implants for active device fabrication, as well as a single metal layer for ohmic Si contacts, on top of a 1 μm thick SiO2 top cladding layer.
  • Metal heaters.

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run for a charge of £35,000. Due to popular demand, we are also offering a reduced design space of 5.5 mm x 4.9 mm for a discounted cost of £20,000.

More information on can be found here.

The mask submission deadline is Friday 1st December 2017.

Tentative Dates for Future CORNERSTONE Calls Released

Provisional announcement dates for future CORNERSTONE fabrications calls have been declared as follows:


Active Device Calls:
Call 9 – 220 nm platform – Announced: Jul. 2018, mask submission deadline: Sep. 2018


Passive Device Calls:
Call 5 – 340 nm platform – Announced: Nov. 2017, mask submission deadline: Jan. 2018
Call 6 – 220 nm platform – Announced: Jan. 2018, mask submission deadline: Mar. 2018
Call 7 – 500 nm platform – Announced: Mar. 2018, mask submission deadline: May. 2018
Call 8 – 220 nm platform – Announced: May. 2018, mask submission deadline: Jul. 2018
Call 10 – 340 nm platform – Announced: Jul. 2018, mask submission deadline: Sep. 2018
Call 11 – 220 nm platform – Announced: Sep. 2018, mask submission deadline: Nov. 2018
Call 12 – 500 nm platform – Announced: Nov. 2018, mask submission deadline: Jan. 2019


Please note that both the proposed platform and announcement date are subject to change.


Access to the CORNERSTONE platform remains free of charge for UK Universities until the end of the September 2019. The platform is also available to anyone outside of the UK for a charge that will be announced at the same time as the design rules.

Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for any queries.

 

CORNERSTONE Multi Project Wafer Run 3 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 3 have been announced. The platform is 500 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches of 160 nm (grating couplers) and 500 nm (strip waveguides).

More information on this run can be found here

The mask submission deadline is Friday 28th July.

CORNERSTONE Second Call Training Course Released

The training course for the CORNERSTONE second call has been published. This course is intended for users who are new to mask design, or for those who want to find out more details about the design rules, fabrication process or submission process.

The training course slides can be downloaded from here.

The mask submission deadline for the second call is Friday 30th June.

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