• A spiral waveguide
  • A photonic chip integrated to a PCB
  • Coupling light into a spiral waveguide
  • A wide-band MMI

LIVE: MPW 12th Call for Passive Devices with Heaters

The design rules for MPW Run 12 (passive devices with heaters on 340 nm SOI) have been announced.

The sign up deadline is Friday 15th March 2019.

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CORNERSTONE @ PIC International

Dr Callum Littlejohns will be presenting a CORNERSTONE talk at the PIC International Conference on 26-27th March 2019 in Brussels, Belgium. There will also be a CORNERSTONE exhibition stand for you to meet the team. 

Schedule

The 2019 CORNERSTONE MPW schedule has been announced.

 

 

 

CORNERSTONE Multi Project Wafer Run 5 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 5 have been announced. The platform is 340 nm Si / 2 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 3 silicon etches of 140 nm (grating couplers), 240 nm (rib waveguides) and 340 nm (strip waveguides). In addition, there will be a 1 µm top cladding SiO2 layer.

The service is free of charge for UK academia. The cost for non-UK academia is £5,000 for a design space of 11.47 mm x 4.9 mm, or £3,500 for a design space of 5.5 mm x 4.9 mm.

The mask submission deadline is Friday 12th January 2018.