CORNERSTONE Multi Project Wafer Run 6 Announced
The design rules for CORNERSTONE multi project wafer (MPW) run 6 on the 220 nm Si / 2 µm BOX SOI platform have been announced. We will offer 3 Si etch processes: 1) a shallow Si etch of 70 nm (grating couplers), 2) an intermediate Si etch of 120 nm (rib waveguides), and 3) a continuation Si etch of a further 100 nm to the BOX layer (strip waveguides). In addition, we will offer two layers for metal heaters (heater filaments and heater contact pads).
Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following options:
Design area: 11.47 mm x 4.9 mm - £10,000.
Design area: 5.5 mm x 4.9 mm - £7,000.
The full design rules and .gds mask template can be found here.
The mask submission deadline is Friday 6th April 2018.
For more information on future calls, visit the Schedule & Cost page.