CORNERSTONE Multi Project Wafer Run 7 Announced
The design rules for CORNERSTONE multi project wafer (MPW) run 7 on the 340 nm Si / 2 µm BOX SOI platform have been announced. We will offer 3 Si etch processes: 1) a shallow Si etch of 140 nm (grating couplers), 2) a full 340 nm etch to the BOX layer (strip waveguides), and 3) a high resolution full 340 nm etch to the BOX layer (photonic crystals) with a minimum feature size of 100 nm.
This call is a result of user feedback informing us of the high demand for high resolution etch layers.
Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:
Design area: 11.47 mm x 4.9 mm = £5,000.
Design area: 5.5 mm x 4.9 mm = £3,500.
The full design rules and .gds mask template can be found here.
The mask submission deadline is Friday 25th May 2018.
For more information on future calls, visit the Schedule & Cost page.