CORNERSTONE Multi Project Wafer Run 8 Announced
The design rules for CORNERSTONE multi project wafer (MPW) run 8 on the 220 nm Si / 2 µm BOX SOI platform have been announced. We will offer 2 Si etch processes: 1) a shallow Si etch of 70 nm (grating couplers), and 2) a partial Si etch of 120 nm (rib waveguides). We will also offer a 1 µm thick silicon dioxide top cladding layer.
This call is intended as a test bed for the next active device call on this platform, later in the year.
Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:
Design area: 11.47 mm x 4.9 mm = £5,000.
Design area: 5.5 mm x 4.9 mm = £3,500.
The full design rules and .gds mask template can be found here.
The mask submission deadline is Friday 31st August 2018.
For more information on future calls, visit the Schedule & Cost page.