Fabrication Underway on CORNERSTONE Multi Project Wafer Run 1

Fabrication at the University of Glasgow and the University of Southampton is underway for the inaugural CORNERSTONE multi project wafer (MPW) run. The process will be carried out on a 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI) platform, and involves 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides).

More information on this run can be found here.

The delivery date for these devices is Wednesday 10th May.