CORNERSTONE Multi Project Wafer Runs 10 & 11 Announced

The design rules for CORNERSTONE multi project wafer (MPW) runs 10 & 11 on the 220 nm Si / 2 µm BOX SOI platform have been announced.

MPW #10 is a passive devices with heaters call; MPW #11 is an active device call.

For these calls there are major changes to the design submission process to align with the introduction of the CORNERSTONE terms and conditions:

All design submissions, even those that are supported by EPSRC funding, must agree with the terms and conditions. Under no circumstances will we accept designs without agreement with the terms.

Therefore, we strongly recommend that the terms and conditions are pre-authorised by your institution prior to the mask submission date.

In order to be eligible to submit a design you must first notify us of your intention to submit a design using the online form found using the link below. This is in order to enable us to prepare the necessary paperwork and plan the fabrication process effectively. The deadline for the notification of intention to submit is Friday 18th January 2019.

www.cornerstone.sotonfab.co.uk/work-with-us/intention-to-submit-form

Under no circumstances will we accept any design submissions for which we have not received prior notification of intention to submit a design.

After completing the intention to submit online form, when you are ready to submit your mask design on or before Friday 1st March 2019, follow the link below to the CORNERSTONE website mask submission page:

www.cornerstone.sotonfab.co.uk/work-with-us/mask-submission-form

Where applicable, any purchase orders must be uploaded to this form. Purchase orders will not be accepted via email.

A process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to these runs is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

MPW #10: Design area: 11.47 mm x 4.9 mm = £10,000; Design area: 5.5 mm x 4.9 mm = £7,000.

MPW #11: Design area: 11.47 mm x 4.9 mm = £35,000; Design area: 5.5 mm x 4.9 mm = £20,000.

The full design rules and .gds mask templates can be on the Design Rules page.

The mask submission deadline for both calls is Friday 1st March 2019.

For more information on future calls, visit the Schedule & Cost page.

CORNERSTONE Multi Project Wafer Run 9 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 9 on the 500 nm Si / 3 µm BOX SOI platform have been announced. We will offer 2 Si etch processes: 1) a shallow Si etch of 160 nm (grating couplers), and 2) a partial Si etch of 300 nm (rib waveguides). We will also offer a 1 µm thick silicon dioxide top cladding layer.

Once again, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

Design area: 11.47 mm x 4.9 mm = £5,000.

Design area: 5.5 mm x 4.9 mm = £3,500.

The full design rules and .gds mask template can be found here.

The mask submission deadline is Friday 30th November 2018.

For more information on future calls, visit the Schedule & Cost page.

CORNERSTONE Multi Project Wafer Run 8 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 8 on the 220 nm Si / 2 µm BOX SOI platform have been announced. We will offer 2 Si etch processes: 1) a shallow Si etch of 70 nm (grating couplers), and 2) a partial Si etch of 120 nm (rib waveguides). We will also offer a 1 µm thick silicon dioxide top cladding layer.

This call is intended as a test bed for the next active device call on this platform, later in the year.

Once again, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

Design area: 11.47 mm x 4.9 mm = £5,000.

Design area: 5.5 mm x 4.9 mm = £3,500.

The mask submission deadline is Friday 31st August 2018.

For more information on future calls, visit the Schedule & Cost page.

CORNERSTONE Multi Project Wafer Run 7 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 7 on the 340 nm Si / 2 µm BOX SOI platform have been announced. We will offer 3 Si etch processes: 1) a shallow Si etch of 140 nm (grating couplers), 2) a full 340 nm etch to the BOX layer (strip waveguides), and 3) a high resolution full 340 nm etch to the BOX layer (photonic crystals) with a minimum feature size of 100 nm.

This call is a result of user feedback informing us of the high demand for high resolution etch layers.

Once again, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a copy of the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, the CORNERSTONE PDK is free of charge if you already have a valid IPKISS license.  

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following cost options:

Design area: 11.47 mm x 4.9 mm = £5,000.

Design area: 5.5 mm x 4.9 mm = £3,500.

The mask submission deadline is Friday 25th May 2018.

For more information on future calls, visit the Schedule & Cost page.

CORNERSTONE Multi Project Wafer Run 6 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 6 on the 220 nm Si / 2 µm BOX SOI platform have been announced. We will offer 3 Si etch processes: 1) a shallow Si etch of 70 nm (grating couplers), 2) an intermediate Si etch of 120 nm (rib waveguides), and 3) a continuation Si etch of a further 100 nm to the BOX layer (strip waveguides). In addition, we will offer two layers for metal heaters (heater filaments and heater contact pads).

For the first time, a process design kit (PDK) has been made available using Luceda’s IPKISS software, subject to purchasing the appropriate license. To obtain a quote for the software and a license key, please contact Luceda by sending an email to This email address is being protected from spambots. You need JavaScript enabled to view it., specifying that you require a license for CORNERSTONE PDK usage. Of course, if you already have a valid license, the PDK can be accessed free of charge.

Access to this run is free of charge for UK research institutes (funded by EPSRC). Overseas universities and industrial companies can access this run with the following options:

Design area: 11.47 mm x 4.9 mm - £10,000.

Design area: 5.5 mm x 4.9 mm - £7,000.

The mask submission deadline is Friday 6th April 2018.

For more information on future calls, visit the Schedule & Cost page.

Research Developed Using CORNERSTONE Published in Nature Communications

A multifunctional silicon photonics integrated circuit that can be programmed to perform a variety of different functions has been developed by researchers from Spain and the UK. The chip was fabricated within the framework of the CORNERSTONE project.

This is “the first photonic integrated chip that enables multiple functionalities by employing a single common architecture”.

The results have been published in Nature Communications.

Reference: Daniel Pérez, Ivana Gasulla, Lee Crudgington, David J. Thomson, Ali Z. Khokhar, Ke Li, Wei Cao, Goran Z. Mashanovich & José Capmany. Multipurpose silicon photonics signal processor core. Nature Communications 8. doi:10.1038/s41467-017-00714-1.

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