CORNERSTONE Multi Project Wafer Run 2 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 2 have been announced. The platform is 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides), with the option of heaters.

More information on this run can be found here.

The mask submission deadline is Friday 30th June.

Multi Project Wafer Run 1 Chips Shipped

Chips from the multi project wafer (MPW) run 1 were shipped to CORNERSTONE users on Monday 8th May to arrive on the specified delivery date of 10th May.

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Fabrication Underway on CORNERSTONE Multi Project Wafer Run 1

Fabrication at the University of Glasgow and the University of Southampton is underway for the inaugural CORNERSTONE multi project wafer (MPW) run. The process will be carried out on a 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI) platform, and involves 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides).

More information on this run can be found here.

The delivery date for these devices is Wednesday 10th May.

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