Tentative Dates for Future CORNERSTONE Calls Released

Provisional dates for future CORNERSTONE fabrications calls have been announced as follows:

 

Active Device Calls:

Call 9 – 220 nm platform – Announced: Jul. 2018, mask submission deadline: Sep. 2018

Call 13 – 340 nm platform – Announced: Jan. 2019, mask submission deadline: Mar. 2019

Passive Device Calls:

Call 7 – 340 nm platform – Announced: Mar. 2018, mask submission deadline: May. 2018

Call 8 – 220 nm platform – Announced: May. 2018, mask submission deadline: Jul. 2018

Call 10 – 500 nm platform – Announced: Jul. 2018, mask submission deadline: Sep. 2018

Call 11 – 220 nm platform – Announced: Sep. 2018, mask submission deadline: Nov. 2018

Call 12 – 340 nm platform – Announced: Nov. 2018, mask submission deadline: Jan. 2019

Call 14 – 220 nm platform – Announced: Jan. 2019, mask submission deadline: Mar. 2019

Call 15 – 500 nm platform – Announced: Mar. 2019, mask submission deadline: May. 2019

 

Please note that both the proposed platform and announcement date are subject to change.

Access to the CORNERSTONE platform remains free of charge for UK Universities until September 2019. The platform is also available to anyone outside of the UK for a charge that can be found on our website www.cornerstone.sotonfab.co.uk.

Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for any queries.

 

CORNERSTONE Multi Project Wafer Run 3 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 3 have been announced. The platform is 500 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches of 160 nm (grating couplers) and 500 nm (strip waveguides).

More information on this run can be found here.

The mask submission deadline is Friday 28th July.

CORNERSTONE Second Call Training Course Released

The training course for the CORNERSTONE second call has been published. This course is intended for users who are new to mask design, or for those who want to find out more details about the design rules, fabrication process or submission process.

The training course slides can be downloaded from here.

The mask submission deadline for the second call is Friday 30th June.

CORNERSTONE Multi Project Wafer Run 2 Announced

The design rules for CORNERSTONE multi project wafer (MPW) run 2 have been announced. The platform is 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI). There will be 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides), with the option of heaters.

More information on this run can be found here.

The mask submission deadline is Friday 30th June.

Multi Project Wafer Run 1 Chips Shipped

Chips from the multi project wafer (MPW) run 1 were shipped to CORNERSTONE users on Monday 8th May to arrive on the specified delivery date of 10th May.

Any feedback from users would be greatly appreciated. Send comments to This email address is being protected from spambots. You need JavaScript enabled to view it..

Fabrication Underway on CORNERSTONE Multi Project Wafer Run 1

Fabrication at the University of Glasgow and the University of Southampton is underway for the inaugural CORNERSTONE multi project wafer (MPW) run. The process will be carried out on a 220 nm Si / 3 µm buried oxide (BOX) silicon-on-insulator (SOI) platform, and involves 2 silicon etches of 70 nm (grating couplers) and 220 nm (strip waveguides).

More information on this run can be found here.

The delivery date for these devices is Wednesday 10th May.

  • 1
  • 2